Heuristic Approach to Circuit Sizing Problem

Circuit sizing problem in application specific analog integrated circuit design is in most cases limited to setting MOSFET channel widths and lengths. It is usually performed by hand by an experienced human designer. As the circuit sizing is an optimization process by its nature, optimization methods could be used. They always lead to one of the minima of the cost function while eventual other minima stay unknown. To reveal different cost minima an optimisation process composed from many individual optimisation runs is proposed. Individual runs are started from various initial points in the parameter space. A particular initial point is determined by a heuristic method which maximises the probability of finding a new cost function minimum in the next run. The optimization process is demonstrated on several real operating amplifier designs. Heuristični pristop k določevanju elementov v integriranih vezjih Ključne besede: računalniško podprto načrtovanje, integrirana vezja, optimizacijski algoritmi, določitev elementov. 1 Introduction Creating a good analogue integrated circuit (or analogue part in a mixed circuit) design is still a hard task, which usually requires senior designer knowledge and skills. There are no predefined libraries of standard cells and networks as in the digital world. Therefore the design of an analogue circuit consisting of a few transistors can be more time consuming than designing a fairly complex digital circuit. Application specific integrated circuit (ASIC) designers also frequently reuse their previous solutions and adapt them to their current needs. A circuit simulator is indispensable in this development procedure. The computers are mainly used to analyze human designs. Initially a suitable circuit configuration is required, which can potentially fulfil the given requirements. This task is mostly left to the designer although several tools partially automating the topology synthesis appeared in the past /1/–/4/. Then the circuit sizing problem has to be solved. One desires such element sizes (e.g. MOSFET channel widths and lengths, capacitors, resistors, etc.) that required circuit properties are met in the most robust manner. Circuit sizing is an optimization process by its nature and one can find quite an extensive literature in this area. Sizing of nominal circuits was considered in /5/–/6/, sizing problems accounting for parameter tolerances (parameter centering) were addressed in /7/–/9/, and worst-case optimization in /10/–/12/. Various optimization tools were developed, like equation based GPCAD /13/, which uses geometric programming formulation of an are addressing the sizing problem from different aspects like process and operating tolerances, mismatch, …